During the wire bonding operation in the assembly of semiconductor devices, or in the subsequent operations where stress is applied to the bond pad, cratering can occur in the structure under the bond because of the weakness in the dielectric structure immediately under the metal layer of the bond pad. Cratering occurs, for example, when the dielectric layer under the bond metal cracks causing the bond pad to separate from the integrated circuit, thereby causing a failure of the chip. Cratering may extend into the field oxide layer below the dielectric layer, or even into the silicon substrate. Thus, although the dielectric layer is necessary for the forming of other structures in the integrated circuit, the dielectric layer does not serve any useful function in the bond pad structure, and it is therefore desirable to subsequently etch the dielectric from under the bond pad to prevent cratering.
In the prior art bond pad formation techniques, a dielectric layer is typically formed on top of a layer of field oxide of the integrated circuit. The dielectric layer is then etched in the bond pad area to avoid cratering. However, during the etching of the dielectric layer, etching into the field oxide may also result. Any etching of the field oxide is undesirable since this typically causes performance, yield, or reliability problems. Also known in the prior art is the use of a polycrystalline silicon layer instead of the dielectric layer under the bond pad. However, because polycrystalline silicon is structurally weak, the same cratering problems also occur.
FIG. 1 illustrates one example of a prior art bond pad structure. Bond pad 10 typically comprises the following layers arranged in the manner shown in FIG. 1: field oxide 20 over silicon 60, first dielectric (D1) layer 21 over field oxide 20, first metal layer 15 over first dielectric layer 21, second dielectric (D2) layer 22 over first metal 15 and first dielectric layer 21, second metal layer 25 over second dielectric layer 22 and first metal layer 15, and passivation layer 50 over second metal layer 25 and second dielectric layer 22.
FIGS. 2a-2k illustrate a prior art semiconductor fabrication process for forming bond pad 10. Referring to FIG. 2a, field oxide 20 is first formed over silicon 60. Following the step of field oxide formation, first dielectric layer 21 is then formed over field oxide 20 as shown in FIG. 2b. FIG. 2c shows the next step of forming first metal layer 15 over first dielectric layer 21. Then as illustrated in FIGS. 2d and 2e, first metal layer 15 is masked with mask layer 23, and then etched to define bond pad site 11.
The process steps shown in FIGS. 2b-2e are then repeated as shown in FIGS. 2f-2k for the formation of second dielectric layer 22 and second metal layer 25. FIG. 2f illustrates forming second dielectric layer 22 over metal layer 15. FIGS. 2g and 2h then show second dielectric layer 22 masked with photoresist mask 16 and etched to define bond pad site 11. FIG. 2i illustrates the next process step of forming second metal layer 25 over etched second dielectric layer 22. Then as illustrated in FIG. 2j, second metal layer 25 is also masked and etched to define bond pad site 11. FIG. 2k shows passivation layer 50 being subsequently formed over etched second metal layer 25 to form bond pad 10.
Ching, et al., Bond Pad Structure Reliability, IEEE/IRPS, CH2508-00, at 64-70 (1988) describes three bond pad structures. One structure comprises a first metal layer over a dielectric layer, the dielectric layer being formed over a field oxide layer, and the field oxide layer formed over a substrate layer. A second bond pad structure shown by Ching differs from the first described bond pad structure by the removal of the dielectric layer from between the first metal layer and the field oxide layer. A third bond pad structure depicted differs from the first bond pad structure by the formation of a titanium tungsten (TiW) layer between the dielectric layer and the metal layer. Ching indicated that of the three described bond pad structures the third bond pad structure with a TiW layer and the dielectric layer intact was the superior bond pad structure to avoid cratering.
With the prior art bond pad formation techniques, cratering can occur during wire bonding or during chip operation due to the inherent weakness of first dielectric layer 21. Dielectric layer 21 is typically selected from one of the following materials such as LTD (Low Temp silicon), BPSG (Boron Phosphorous Silicon Glass), or other silicon glass. Removing dielectric layer 21 prevents cratering from occurring on the integrated circuit. However, in the prior art semiconductor fabrication process, removing dielectric layer 21 may result in damaging field oxide layer 20, causing performance, yield or reliability problems with the integrated circuit. It is therefore desirable to provide a semiconductor fabrication process for preventing cratering without damage to the field oxide layer.